Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/32588
DC Field | Value | |
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dc.title | Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing | |
dc.contributor.author | CHAN, LAP | |
dc.contributor.author | CHA, CHER LIANG | |
dc.contributor.author | LEE, TECK KOON | |
dc.date.accessioned | 2012-05-02T02:27:26Z | |
dc.date.available | 2012-05-02T02:27:26Z | |
dc.date.issued | 2001-03-27 | |
dc.identifier.citation | CHAN, LAP,CHA, CHER LIANG,LEE, TECK KOON (2001-03-27). Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/32588 | |
dc.description.abstract | A method of forming trenches having different depths for use in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing stop of silicon nitride is deposited. An oxide layer is grown overlying the silicon substrate. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned first trenches. A polysilicon layer is deposited overlying the oxide layer and filling the openings for the planned first trenches. The polysilicon layer is polished down to the top surface of the oxide layer such that the polysilicon layer remains only in the openings of the planned first trenches. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned second trenches. The silicon substrate and the polysilicon layer are simultaneously etched to complete the first trenches and the second trenches, with the second trenches deeper than the first trenches, and with the oxide layer a hard mask, and the integrated circuit device is completed. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US6207534 | |
dc.source | PatSnap | |
dc.type | Patent | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.identifier.isiut | NOT_IN_WOS | |
dc.description.patentno | US6207534 | |
dc.description.patenttype | Granted Patent | |
dc.contributor.patentassignee | CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (SINGAPORE, SG) | |
dc.contributor.patentassignee | NATIONAL UNIVERSITY OF SINGAPORE | |
Appears in Collections: | Staff Publications |
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US6207534.PDF | 89.8 kB | Adobe PDF | OPEN | Published | View/Download |
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