Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/32582
DC Field | Value | |
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dc.title | Method of making spiral-type RF inductors having a high quality factor (Q) | |
dc.contributor.author | CHU, SHAU-FU SANFORD | |
dc.contributor.author | CHEW, KOK WAI JOHNNY | |
dc.contributor.author | CHUA, CHEE TEE | |
dc.contributor.author | CHA, CHER LIANG | |
dc.date.accessioned | 2012-05-02T02:27:21Z | |
dc.date.available | 2012-05-02T02:27:21Z | |
dc.date.issued | 2000-10-31 | |
dc.identifier.citation | CHU, SHAU-FU SANFORD,CHEW, KOK WAI JOHNNY,CHUA, CHEE TEE,CHA, CHER LIANG (2000-10-31). Method of making spiral-type RF inductors having a high quality factor (Q). ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/32582 | |
dc.description.abstract | A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal line and the dielectric layer. The intermetal dielectric layer is patterned whereby a plurality of openings are made through the intermetal dielectric layer to the semiconductor substrate. Thereafter, an oxide layer is deposited overlying the intermetal dielectric layer and capping the plurality of openings thereby forming air gaps within the intermetal dielectric layer. A metal plug is formed through the oxide layer and the intermetal dielectric layer to the metal line. A metal layer is deposited overlying the oxide layer and patterned to form an inductor wherein a portion of the inductor contacts the metal line through the metal plug to complete formation of an inductor utilizing air as an underlying barrier in the fabrication of an integrated circuit. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US6140197 | |
dc.source | PatSnap | |
dc.type | Patent | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.identifier.isiut | NOT_IN_WOS | |
dc.description.patentno | US6140197 | |
dc.description.patenttype | Granted Patent | |
dc.contributor.patentassignee | CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (SINGAPORE, SG) | |
dc.contributor.patentassignee | NATIONAL UNIVERSITY OF SINGAPORE | |
Appears in Collections: | Staff Publications |
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US6140197.PDF | 89.06 kB | Adobe PDF | OPEN | Published | View/Download |
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