Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/28276
Title: Fractional-N DLL for clock synchronization
Authors: QIU LIN
Keywords: Delay-locked loop, fractional-N, clock synchronization, low jitter, delta-sigma modulator, mixed IC design
Issue Date: 22-Apr-2008
Source: QIU LIN (2008-04-22). Fractional-N DLL for clock synchronization. ScholarBank@NUS Repository.
Abstract: This thesis presents on the design of a fractional-N delay locked loop (DLL)circuit for clock synchronization in the transceiver system. A delta-sigma modulator is integrated into the DLL design to achieve low noise and low jitter performance. It is verified through the behavior model simulation that this DLL can provide fine phase resolution, wide operation range and low jitter performance. The whole architecture is implemented in 0.35 um CMOS and is able to handle input clock frequency range from 10MHz~200MHz. This novel technique can also be used for a variety of applications which requires accurate timing delay or fine tuning resolution.
URI: http://scholarbank.nus.edu.sg/handle/10635/28276
Appears in Collections:Master's Theses (Open)

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