Fractional-N DLL for clock synchronization

Abstract

This thesis presents on the design of a fractional-N delay locked loop (DLL)circuit for clock synchronization in the transceiver system. A delta-sigma modulator is integrated into the DLL design to achieve low noise and low jitter performance. It is verified through the behavior model simulation that this DLL can provide fine phase resolution, wide operation range and low jitter performance. The whole architecture is implemented in 0.35 um CMOS and is able to handle input clock frequency range from 10MHz~200MHz. This novel technique can also be used for a variety of applications which requires accurate timing delay or fine tuning resolution.