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Title: Compliant Chip-to-Package Interconnects for Wafer Level Packaging
Authors: LIAO EBIN
Keywords: compliant interconnects, wafer level packaging, multi-copper-column interconnects, planar microspring interconnects, thermomechanical reliability
Issue Date: 20-Mar-2008
Source: LIAO EBIN (2008-03-20). Compliant Chip-to-Package Interconnects for Wafer Level Packaging. ScholarBank@NUS Repository.
Abstract: In this thesis, two novel compliant chip-to-package interconnects, Multi-Copper-Column (MCC) and Planar Microspring, are developed to address the needs of next-generation microelectronics systems. The major contribution of this thesis is as follows: 1) An analytical model reveals the reliability improvement of compliant interconnects over conventional counterparts. The geometric dependence of mechanical compliance and electrical parasitics are investigated. The planar microspring shape is optimized in terms of compliance and electrical performance. 2) Combining thin-film processing and surface micromachining technology, high-aspect-ratio (~6) 40um-pitch MCC and free-hanging 60um-pitch Planar Microspring interconnects are successfully prototyped. The electrical functionality under low- and high-frequency conditions are experimentally verified. 3) A systematic method is developed to integrate solder shape evolution with reliability analysis. A quantitative model is further established to explain the complex influence of non-solder component compliance upon solder joint reliability. Equivalent lumped circuit model of interconnect is established and matches well with direct simulation.
Appears in Collections:Ph.D Theses (Open)

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