Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

Abstract

This thesis derives efficient partial element equivalent circuit (PEEC) models in homogeneous media, dielectric mesh media, multilayered media and applies the models for the development of a novel elastomer mesh test interface for wafer level packages (WLP) operating at multigigahertz frequencies given the tight geometrical constraints of fine pitch (of the order of 100 micron) off-chip interconnects and large device pin counts (of the order of thousands). An improved PEEC model is first derived for homogeneous media through circuit scaling techniques. The model is extended to lossy silicon substrates using the theory of complex images. The PEEC model is developed for treating the dielectric elastomer mesh which is used as a probe substrate. The local interaction between the dielectric and metal is factored into the electric field integral equation for accurate representation of the circuit element. The model is then applied to multilayer dielectrics. The validity of the modeling as well as the prototype system is demonstrated with simulation and measurement results.