Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/27821
Title: Development of low on state resistance power devices
Authors: GAN KIAN PAAU
Keywords: Superjunction devices, DMOS devices, power devices, ideal silicon limit, PFVDMOS, OBVDMOS
Issue Date: 11-Jan-2004
Source: GAN KIAN PAAU (2004-01-11). Development of low on state resistance power devices. ScholarBank@NUS Repository.
Abstract: Superjunction devices were recently proposed to overcome on state resistance limitation of power MOSFET in scaling higher breakdown voltage. The pioneer technology used in superjunction devices was complicated involving costly multiple epitaxy processes. By using a thin in-between oxide as diffusion barrier between alternating p and n layers, a Poly-Flanked VDMOS (PFVDMOS) was proposed and developed to enable the scaling of p and n layers. However PFVDMOS suffers from the difficult task of matching n and p doping. Oxide-Bypassed VDMOS (OBVDMOS) was next proposed and developed to avoid this problem by having a metal-thick-oxide (MTO) in place of p column that relies on oxide thickness control instead of doping control. With a specific on state resistance, Ron,sp value of 3.92 mW-cm2 at 184 V, a trench gate OBVDMOS was capable of achieving a Ron,sp lower than ideal silicon limit with careful trench gate design.
URI: http://scholarbank.nus.edu.sg/handle/10635/27821
Appears in Collections:Master's Theses (Restricted)

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