Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/21000
Title: Nickel Silicide Interface Engineering for Contact Resistance Reduction in Nanoscale CMOS Technology
Authors: WONG HOONG SHING
Keywords: NiSi, Interface, contact resistance, CMOS, Selenium, Antimony
Issue Date: 21-Dec-2009
Source: WONG HOONG SHING (2009-12-21). Nickel Silicide Interface Engineering for Contact Resistance Reduction in Nanoscale CMOS Technology. ScholarBank@NUS Repository.
Abstract: CMOS transistors? scaling beyond 32 nm technology generations faces immense challenges in achieving device performance enhancement. Due to the rapid shrinkage of gate pitch and wide-spread implementation of strain engineering in CMOS devices, external series resistance REXT has become a larger component as compared to channel resistance RChannel in the total device resistance RTotal. In general, the REXT of a nanoscale MOSFET is dominated by silicide contact resistance RCSD. Hence, innovative RCSD reduction approaches with the ease of CMOS integration have to be actively pursued to continue improving the device performance. Numerous silicide contact technologies had been experimentally demonstrated and show great promises in reducing the RCSD and REXT. Dopant segregation contact technology had been a promising solution to reduce the REXT of nanoscale CMOS devices. It involved the dopants pile-up process during silicidation to reduce the Schottky barrier height ?B. In this work, novel method to introduce solid antimony (Sb) dopant and nickel for forming low RCSD silicide contact was explored. During silicidation, solid Sb was segregated at the NiSi/n-Si interface, reducing electron ?B from 0.67 eV to 0.074 eV. The integration of Sb segregation contact technology with bulk n-MOSFET led to a significant REXT reduction and drive current enhancement. Alternative silicide contact technology using Se implant and segregation was explored to reduce the ?B of NiSi formed on n-type Si and n-type silicon-carbon (Si:C) layer. Low electron ?B of ~0.1 eV was achieved without degrading the silicide material qualities. A proposed hypothesis suggested that the segregated Se at the silicide interface help to pin the metal Fermi level close to the conduction band of Si which contributes to low electron ?B formation. This work also demonstrated the integration of Se segregation contact technology with strained silicon-on-insular (SOI) n-MOSFET with Si:C stressors and ultra-thin body n-MOSFET. Significant drive current enhancement was achieved as compared to the control devices without Se segregation. This was attributed to RCSD reduction, elucidating the effectiveness of Se segregation contact technology for extending device performance. In this work, n- and p- channel quantum wire field-effect transistor (QWFET) with dopant-segregated metallic source and drain (S/D) regions was experimentally demonstrated. Significant REXT reduction was observed, leading to pronounced device performance enhancement. Further characterization indicates injection velocity increment for QWFET with dopant-segregated metallic S/D, possibly contributing to performance improvement. Comparable short channel characteristics were also observed for QWFET with and without dopant-segregated metallic S/D. This work also investigates the impact of strain engineering on p-channel QWFET. Higher device performance enhancement was clearly shown for p-channel QWFET with reduced REXT. These results indicate that silicide contact technology holds great promises for further CMOS performance enhancement.
URI: http://scholarbank.nus.edu.sg/handle/10635/21000
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