Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/17747
Title: IC design, UWB synchronization circuit
Authors: TOH WEI DA
Keywords: Clock and Data Recovery, Clock Drift, Digital Baseband, Synchronization, Ultra Wideband (UWB), Wireless Transceiver
Issue Date: 30-Sep-2009
Source: TOH WEI DA (2009-09-30). IC design, UWB synchronization circuit. ScholarBank@NUS Repository.
Abstract: In conventional radio frequency (RF) transceivers, clock drift problem exists between transmitter and receiver due to the different system clock employed. Therefore, clock and data recovery (CDR) circuitry will be required to recover the received data correctly. Phase locked loop (PLL) and delay locked loop (DLL) are very commonly used analog building blocks for clock and data recovery (CDR) applications. Another popular timing recovery technique involves the use of analog-to-digital converter (ADC), coupled with digital signal processing algorithm. However, these techniques are very power consuming and not easily scalable with Complementary Metal¿Oxide¿Semiconductor (CMOS) technology. A novel low power, all digital timing recovery technique to be used together with the ultra-wideband (UWB) radio frequency front-end is therefore proposed in this work, which achieves low power consumption and is easily scalable. In addition, the voltage controlled oscillator (VCO) employed in UWB transmitter is susceptible to process, supply voltage and temperature (PVT) variations which can lead to spectral shift and variations which violate the UWB Federal Communications Commission (FCC) spectral mask. A digital calibration technique is also proposed and implemented in this work to tackle the problem to achieve accurate transmitting frequency and pulse width calibration.
URI: http://scholarbank.nus.edu.sg/handle/10635/17747
Appears in Collections:Master's Theses (Open)

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