Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/17331
Title: Schottky barrier engineering for contact resistance reduction in nanoscale CMOS transistors
Authors: MANTAVYA SINHA
Keywords: Metal-semiconductor contacts, Schottky barrier height, contact resistance, FinFETs, aluminum implant, acceptor-type trap levels
Issue Date: 4-Jan-2010
Source: MANTAVYA SINHA (2010-01-04). Schottky barrier engineering for contact resistance reduction in nanoscale CMOS transistors. ScholarBank@NUS Repository.
Abstract: This thesis involves the development of simple and low cost solutions to reduce contact resistance in CMOS FETs. Contact resistance at the interface between silicide and heavily-doped source/drain (S/D) region is a major fraction of the total parasitic series resistance. Series resistance is a bottleneck for device performance at the sub-22 nm technology node, where multiple-gate transistors (for e.g., FinFETs) are slated to be introduced. It is an even bigger issue in FinFETs with narrow fin width. New materials and processes are needed to achieve target contact resistance and contact resistivity levels determined by the ITRS roadmap. Contact resistivity at the interface between metal silicide (for e.g., nickel-silicide NiSi) and heavily-doped source and drain region in a MOSFET is dependent exponentially on the Schottky barrier height at the interface. In this thesis, novel ion-implantation based techniques to modulate the Schottky barrier height have been developed. These have been demonstrated in FinFETs with S/D made of silicon (for p-FETs and n-FETs), silicon-germanium SiGe (for strained p-FETs) or silicon-carbon Si:C (for strained n-FETs). Only nickel(Ni)-based silicides (either pure NiSi or a silicide formed of an alloy of Ni and a rare-earth metal) are used in this work for their ease of adoption by the semiconductor industry with minimal process and cost overheads. Furthermore, substrate engineering has also been studied for contact resistance reduction in n-FETs with Si:C S/D. In particular, through ion-implantation of impurity elements at the interface between metal-silicide and the S/D material of MOSFETs, modulation of Schottky barrier height is demonstrated. A range of materials (impurity elements), such as aluminum (Al), cobalt (Co), cadmium (Cd), zinc (Zn), and magnesium (Mg) are screened to investigate their possible application in lowering the effective hole Schottky barrier height of NiSi on p-Si. With Al implant and segregation,a 70% lowering of hole Schottky barrier height of NiSi on p-Si is achieved. The mechanism responsible for the modulation of Schottky barrier height is also studied through extensive material characterization. When the Al implant technology is integrated in the S/D of p-FinFETs, 15% enhancements in drive current is achieved. Furthermore, the Al implant technology is also developed for strained p-FETs with SiGe S/D. The achievement of one of the lowest reported hole Schottky barrier height for NiSiGe on SiGe, of 0.068 eV is demonstrated. Finally, two novel single-silicide integration schemes are developed that demonstrate independent and simultaneous contact resistance reduction in both, p- and n- channel FETs. In the first approach, a silicide formed of an alloy of Ni and dysprosium (Dy) is demonstrated, coupled with the Al implant technology. The second approach demonstrates a single-mask integration scheme using a double-species implant of Al and sulfur (S) to achieve dual near-band-edge barrier heights. The compensation effect of Al and S implants is studied to achieve significant contact resistance reduction and drive current enhancement in both p- and n- channel FinFETs.
URI: http://scholarbank.nus.edu.sg/handle/10635/17331
Appears in Collections:Ph.D Theses (Open)

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