Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/16823
DC Field | Value | |
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dc.title | A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer | |
dc.contributor.author | LAU WEE YEE WENDY | |
dc.date.accessioned | 2010-04-15T18:35:16Z | |
dc.date.available | 2010-04-15T18:35:16Z | |
dc.date.issued | 2009-08-04 | |
dc.identifier.citation | LAU WEE YEE WENDY (2009-08-04). A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/16823 | |
dc.description.abstract | The design of a high-frequency fractional-N frequency synthesizer, which offers technological robustness, versatility, fast locking capability, low noise contribution, superior integration capacity and multi-modulus flexibility, for use in the 2450MHz band (and also support the 910MHz band) operation using a 0.35µm CMOS technology is demonstrated. The design focuses on the prescaler, which is one of the critical speed bottlenecks for phase-locked loop (PLL). A quad-modulus prescaler with programmable division ratios of 16/17/20/21 is implemented using differential current mode logic (CML) latches, OR-embedded CML latches and dynamic OR-gates to minimize dynamic power consumption, avoid glitches and jitter due to mismatch in input signalsâ phases whilst maintaining high-frequency and fast-switching capabilities. The prescaler is able to operate up to 3.87GHz with Iac=21.09mA, and 3.05GHz with Iac=18.09mA. The entire synthesizer design draws 21.34mA from a 3.3V supply, and occupies an area of approximately 0.699mm2. | |
dc.language.iso | en | |
dc.subject | quad-modulus prescaler, current mode logic (CML), CMOS, high-frequency, fractional-N frequency synthesizer, phase-locked loop (PLL) | |
dc.type | Thesis | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.contributor.supervisor | YAO LIBIN | |
dc.description.degree | Master's | |
dc.description.degreeconferred | MASTER OF ENGINEERING | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Master's Theses (Open) |
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File | Description | Size | Format | Access Settings | Version | |
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LauWYW.pdf | 2.76 MB | Adobe PDF | OPEN | None | View/Download |
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