Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/16578
Title: System-on-Chip design of a high performance low power full hardware cabac encoder in H.264/AVC
Authors: TIAN XIAOHUA
Keywords: CABAC, H.264, video compression, SoC, low power, ASIC
Issue Date: 20-Mar-2009
Source: TIAN XIAOHUA (2009-03-20). System-on-Chip design of a high performance low power full hardware cabac encoder in H.264/AVC. ScholarBank@NUS Repository.
Abstract: Context-based Adaptive Binary Arithmetic Coding (CABAC) and Rate-Distortion Optimization (RDO) are two important techniques that enhance compression efficiency of H.264/AVC. This work focuses on high performance ASIC design of CABAC encoder IP targeting at Main Profile of H.264/AVC with full RDO support.This design follows a SoC-based design flow. With careful top-level functional partitioning and exploring of various design methodologies, CABAC encoder performance is enhanced significantly. It is the only reported design that achieves high processing speed of real time CIF coding in full RDO mode and HDTV coding in RDO-off mode. It achieves best compression efficiency and lowest power consumption (0.79 mW at HDTV 8.9Mbps RDO-off mode). Only this work provides complete SoC-based IP solution of CABAC encoder that efficiently supports different video coding configurations and extends design application range. The work enhances performance of both CABAC encoder and H.264 video coding system, and achieves global performance optimization.
URI: http://scholarbank.nus.edu.sg/handle/10635/16578
Appears in Collections:Ph.D Theses (Open)

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