Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/16572
Title: Design and implementation of Asynchronous SRAM
Authors: CHENG XIANG
Keywords: SRAM, asynchronous, four-phase, dual-rail, Muller C, delay-insensitive
Issue Date: 4-Aug-2009
Source: CHENG XIANG (2009-08-04). Design and implementation of Asynchronous SRAM. ScholarBank@NUS Repository.
Abstract: Asynchronous circuits use handshaking protocol instead of clock between components to make the necessary communication and synchronization. Compared with synchronous circuit, asynchronous circuits have some advantages such as robustness towards variations, better modularity, and low power consumption. Some implementations have been reported to use off-the-shelf synchronous SRAM to emulate asynchronous SRAM which sometimes still costs unnecessary power. An intrinsic asynchronous SRAM using four-phase dual-rail protocol and event-trigger mechanism has been designed and implemented for the asynchronous 8051 microcontroller. Two versions of asynchronous SRAM which are 16*8 bits and 128*8 bits SRAM have been fabricated with AMS 0.35um double-poly four-metal CMOS technology. Experimental testing shows the SRAMs are working well at the power supply between 0.81V and 3.5V.
URI: http://scholarbank.nus.edu.sg/handle/10635/16572
Appears in Collections:Master's Theses (Open)

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