Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/16052
Title: Micro-architecture level low power design for microprocessors
Authors: XIA XIAOXIN
Keywords: low power design, microarchitecture, microprocessor
Issue Date: 5-Sep-2008
Source: XIA XIAOXIN (2008-09-05). Micro-architecture level low power design for microprocessors. ScholarBank@NUS Repository.
Abstract: Power dissipation is becoming a crucial design constraint for modern processors. This thesis first investigates power dissipation sources in the microprocessor and discusses various power reduction technologies. Then, it presents a realistic analysis model to address possible power reduction opportunities during application execution. Using this model, it employs a micro-architecture parameter (IPC) as the performance indicator and proposes two IPC-driven low-power designs. One is an online interval-based identification and prediction design, which uses IPC to quantify the current intervalb s performance activity level and predict the coming interval at which certain power-performance trade-off would be profitable. The other one is an offline code analysis and reconfiguration design, which identifies code sections having appropriate IPC values and profiles them to dynamically scale voltage and frequency of the processor to reduce power dissipation. We also presented two methods to identify related micro-architecture parameters.
URI: http://scholarbank.nus.edu.sg/handle/10635/16052
Appears in Collections:Ph.D Theses (Open)

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