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Title: Selective EPI process for advanced CMOS devices
Keywords: SiGe, SiC, SiGeC, Epitaxy, Critical thickness, Substitutional carbon
Issue Date: 17-Nov-2008
Source: CHOI KYU JIN (2008-11-17). Selective EPI process for advanced CMOS devices. ScholarBank@NUS Repository.
Abstract: Strained silicon technologies have been attracted attention to high performance application for last few years, because biaxial strained channel engineering enhances carrier mobility and transistor drive current. The strained Si/SiGe material system can utilize the 4% lattice mismatch between Si and Ge to provide improved carrier transport in PMOS channels and consequently advanced CMOS devices. Recently, SiC source/drain has been studied for device performance in NMOS because a pseudomorphic SiC films are under tensile strain when grown on silicon due to a small size of carbon. We have investigated the epitaxial growth of SiGe, SiC, and SiGeC alloys on a Si 100) surface by ultra high vacuum chemical vapor deposition (UHVCVD) using Si2H6, GeH4 and SiH3CH3 for application of advanced CMOS devices. We have studied growth rate, Ge concentration and critical thickness (SiGe alloy) and growth rate, selectivity, and C concentrations after implantation and annealing (SiC & SiGeC alloy).
Appears in Collections:Master's Theses (Open)

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