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Title: High-speed flash adc design
Authors: GU JUN
Keywords: High-speed comparator design, high-speed ADC design, flash ADC design, bipolar IC design, SiGe HBT technology.
Issue Date: 11-Jan-2007
Citation: GU JUN (2007-01-11). High-speed flash adc design. ScholarBank@NUS Repository.
Abstract: As Ultra Wideband (UWB) Communications become more and more popular, the design of analog-to-digital converters (ADC) used in this area also requires more attention. The ADC sampling speed will be the most critical issue. Flash ADCs are known to be one of the fastest possible converters. But the performance of a flash ADC strongly depends on that of their constituent comparators. This thesis presents the design and analysis of two ultra high-speed bipolar comparators based on master-slave architecture and the analog part of a flash ADC based on the comparator with improved bias scheme. Master-slave structure for the comparators is used to improve metastability behavior and reduce minimum differential input voltage. Implemented in a 0.35-I?m SiGe BiCMOS process, both of the comparators designed consume moderate power with sampling speed of 16 GHz and the analog part of the flash ADC works at a sampling speed of 6 GSample/s with resolution of 5 bits.
Appears in Collections:Master's Theses (Open)

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