Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/15547
Title: Functional unit selection in microprocessors for low power
Authors: PAN YAN
Keywords: Low Power Microprocessor Data Path Design
Issue Date: 21-Nov-2006
Source: PAN YAN (2006-11-21). Functional unit selection in microprocessors for low power. ScholarBank@NUS Repository.
Abstract: In this work, we focused on dynamic power reduction in superscalar microprocessors by exploiting the laxity in the execution of instructions. The objective is to execute instructions whose result is not immediately referred to in slower and power frugal Functional Units (FU). We developed two instruction filtering algorithms to make the FU selection for instructions depending on their urgency without modifying the sequence of the object codes. To further reduce power dissipation, a scheduling algorithm is proposed so as to expose more instructions for power-frugal execution. Simulation shows that the scheduling algorithm can improve the execution efficiency, as measured by Instruction Per Cycle (IPC), while still reduces significant amount of energy. Prospect of issuing 30% to 40% of integer ALU instructions to power-frugal ALUs has been shown with the benchmarks, which implies a power reduction of 15% to 20% of power reduction in the integer ALUs.
URI: http://scholarbank.nus.edu.sg/handle/10635/15547
Appears in Collections:Master's Theses (Open)

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
Thesis_Final.pdf1.04 MBAdobe PDF

OPEN

NoneView/Download

Page view(s)

173
checked on Jan 22, 2018

Download(s)

160
checked on Jan 22, 2018

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.