Bed of nails(B0N) - 100 microns pitch wafer level off-chip interconnects for microelectronic packaging applications

Abstract

The demand for interconnection density both on integrated circuit (IC) and packages increases tremendously as microsystems continue to move towards high speed and microminiaturization technologies. In order to meet the silicon device performance, number of I/Os needs to increase by 15% every year and the cost per pin needs to decrease by 10% every year to match the silicon productivity and cost. In the near future, the necessity for higher I/O count, 10,000 per IC chip requiring fine pitch of <100A?m would increase as the IC technology shift towards the nano ICs with feature size of <90nm. In current approaches for chip-to-package interconnections at fine pitch solder interconnects number of limitations was observed. The main failure in these solder interconnects are due to the CTE mismatch between the Si chip and substrate. Especially in fine pitches, assembly yield and process costs are found to be higher due to the low stand off height and less solder volume. Thus, the present interconnection technologies cannot meet the essential requirements of reliability, cost, performance and manufacturability. Hence, in this present work, a new technology namely Bed of Nails (BoN) interconnections was conceived, designed, fabricated and tested to meet the above requirements. The fabrication uses conventional wafer level process, hence it is convenient to mass produce these interconnects. This work also highlights the challenges in high aspect ratio lithography process (50A?m diameter and 100-130A?m height) and electroplating of copper nails. The test chips were designed and fabricated based on the optimized process developed. Two different test chips of 10 mm ?? 10 mm and 20 mm ?? 200 mm sizes were fabricated. The fabricated test chip with BoN interconnects was assembled on conventional test board using Karl-Suss flip chip bonder (FC-150). This interconnects were subjected to thermal cycle test as per the JEDEC standards. Results obtained clearly showed that BoN interconnects are at least better by a factor two compared to the conventional solder interconnects. Failure modes of the samples were analyzed using scanning electron microscopy and major failures were observed in the bulk solder. These failures can be further reduced by using solder of better properties. The wafer level interconnects Bed of Nails developed in this study can be implemented for fine pitch interconnect schemes between Si chip and substrate.