Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/14735
Title: A CMOS DB-linear VGA with DC offset cancellation for direct-conversion receiver
Authors: YAN JIANGNAN
Keywords: dB-linear, DC offset cancellation, I/Q mismatch, I/Q tuning loop, Pre-distortion compensation, VGA
Issue Date: 18-Aug-2005
Source: YAN JIANGNAN (2005-08-18). A CMOS DB-linear VGA with DC offset cancellation for direct-conversion receiver. ScholarBank@NUS Repository.
Abstract: In this thesis, a CMOS dB-linear variable gain amplifier (VGA) with a novelI/Q tuning loop to remove DC offset for direct-conversion receiver has beendesigned in a 0.35I?m CMOS technology.The dB-linear VGA comprises a linear VGA and a novel pseudo-exponentialvoltage circuit. Different VGA and pseudo-exponential circuit have been studied.The proposed circuit is a differential source degenerated VGA and a Taylora??sseries expansion based pseudo-exponential voltage circuit, which has beendesigned, simulated, and tested.Different DC offset cancellation methods have been investigated and a novelI/Q tuning loop is presented. DC offset sense issues have been discussed andsolutions are presented. Block level simulation, circuit level simulation andmeasurement result are explained.This dB-linear VGA provides a variable gain of 60dB while maintaining its 3dB bandwidth greater than 2.5 MHz. DC offset rejection is 50 dB. The overallIIP3 and IIP2 is 12.165dBm and 40.7dBm, respectively.
URI: http://scholarbank.nus.edu.sg/handle/10635/14735
Appears in Collections:Master's Theses (Open)

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
YanJN.pdf1.18 MBAdobe PDF

OPEN

NoneView/Download

Page view(s)

362
checked on Dec 11, 2017

Download(s)

1,050
checked on Dec 11, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.