Design of efficient constrained codes and parity-check codes for perpendicular magnetic recording channels

Abstract

In this thesis, we investigate two strategies for designing efficient constrained codes and parity-check codes to improve the bit error rate performance on perpendicular magnetic recording channels. First, we present the combination of a strong distance-enhancing code with a novel parity-check code. The design of the novel constrained parity-check code results in a post-processor that is computationally much simpler than conventional post-processors. We also examine the optimality of the post-processors used in current systems. Secondly, an original method is proposed for identifying high-capacity runlength constraints for parity-based post-processors based on maximum a posteriori decision rule. This method is based on a reduced complexity computer search of runlength constraints that separate the probabilities of dominant error events. These constraints serve as the basis for designing efficient high-rate constrained parity-check codes.