Please use this identifier to cite or link to this item:
Title: A low power design for arithmetic and logic unit
Authors: NG KAR SIN
Keywords: low power, instruction scheduling, computer architecture
Issue Date: 30-Dec-2004
Citation: NG KAR SIN (2004-12-30). A low power design for arithmetic and logic unit. ScholarBank@NUS Repository.
Abstract: The aim of this project was to create a microprocessor that consumed as little power as possible, with little or no compromise in its performance. This thesis explores the ways power consumption can be reduced without affecting performance, by using slow functional units to execute instructions. Slow functional units consume lesser power than the fast ones. They can be used as long as no hazards or stalls occur.The proposed low power ALU design comprises a Control Unit, a Register File and a set of slow and fast functional units. An offline software schedule was developed to analyze instruction order and schedule the use of the slow functional units accordingly. Because the functional units operate different performance levels, instructions that are in-orderly issued may be out-of-orderly executed. To prevent this, the Control Unit is used to synchronize instruction issues and retirements, and update the Register File at appropriate times. Hence, the ALU is capable of attaining low power operations.
Appears in Collections:Master's Theses (Open)

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
A Low power Design for Arithmetic and Logic Unit.pdf1.47 MBAdobe PDF



Page view(s)

checked on Nov 4, 2018


checked on Nov 4, 2018

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.