Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/14353
Title: Advanced gate stack for sub-0.1 (mu)m CMOS technology
Authors: YU HONGYU
Keywords: CMOS, high-K, metal-gate, tunneling-curent
Issue Date: 28-Feb-2005
Source: YU HONGYU (2005-02-28). Advanced gate stack for sub-0.1 (mu)m CMOS technology. ScholarBank@NUS Repository.
Abstract: The scope of this thesis emphasizes on studies of advanced gate stack for future nano-meter scale CMOS device application. Firstly, the materials properties of ALD (HfO2)x(Al2O3)1-x high-K gate dielectrics were investigated, including their band alignment to (100)Si, and their thermal stability on Si substrate. Secondly, a systematic study on novel HfN metal gate electrode for advanced CMOS devices applications is reported for the first time. Thirdly, a study on metal gate work function thermal stability is presented. A metal-dielectric interface model taking the role of extrinsic states into account was proposed to qualitatively explain the dependence of metal work function on annealing process. Finally this thesis presents a systematic study of hole tunneling current through ultrathin oxide and oxynitride gate dielectrics in p?MOSFETa??s devices.
URI: http://scholarbank.nus.edu.sg/handle/10635/14353
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