Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/14290
Title: Design of high speed 1:4 demultiplexer for optical communication systems
Authors: SUN PINPING
Keywords: demultiplexer , optical communication, CMOS, BiCMOS, common-mode logic, emitter-follower logic
Issue Date: 8-Oct-2004
Source: SUN PINPING (2004-10-08). Design of high speed 1:4 demultiplexer for optical communication systems. ScholarBank@NUS Repository.
Abstract: Two integrated circuit designs are presented in this thesis.One is a 2.5-Gb/s 1:4 Demultiplexer (DEMUX) circuit which has been implemented in a standard 0.18-um CMOS process for optical fiber communication systems. A MOS Current-Steering (MCS) latch is used in the design of the high-speed D-flip-flops. The designed DEMUX is able to operate in the frequency range from 1 a?? 2.5 GHz with a large phase margin, and consumes 137 mA from a 2.08V power supply. The other is a 10-Gb/s 1:4 Demultiplexer (DEMUX) circuit which has been implemented in a 0.25-um SiGe:C BiCMOS process. A two-level series gating differential emitter-coupled logic is used in the design of the high-speed D-flip-flops. The circuit operates from a single 2.5-V supply and consumes 110mA (including 50I? buffers).
URI: http://scholarbank.nus.edu.sg/handle/10635/14290
Appears in Collections:Master's Theses (Open)

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