Please use this identifier to cite or link to this item:
Title: Combined instruction scheduling and register allocation
Keywords: Instruction Level Parallelism, register allocation, instruction scheduling, phase ordering problem, simultaneously live ranges, spill code insertion
Issue Date: 16-Aug-2004
Citation: KHAING KHAING KYI WIN (2004-08-16). Combined instruction scheduling and register allocation. ScholarBank@NUS Repository.
Abstract: In compilers for machines with instruction-level parallelism, the phases of instruction scheduling and register allocation can be disaffected phases. Negative effects can be detected whichever phase is executed first. In order to take the best advantage of the Instruction Level Parallelism (ILP), compilers need to minimize both delays due to memory latency and register usage. Unfortunately, when register allocation is done first, unnecessary dependencies are added. Although spill code is minimized, the execution time of the program may increase. When instruction scheduling is executed first, an efficient schedule is generated. However, the code motion that occurs after instruction scheduling generally increases spill code. In order to solve this phase ordering problem, attempt has been made to use several approaches. First, this research studies optimal and near optimal instruction scheduling and register allocation separately. Then, these two phases are combined to obtain both optimal instruction scheduling and lower spill code placement.
Appears in Collections:Master's Theses (Open)

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
KyiWinKK.pdf531.06 kBAdobe PDF



Page view(s)

checked on Nov 10, 2018


checked on Nov 10, 2018

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.