Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/137752
Title: DESIGN SPACE EXPLORATION TECHNIQUES FOR FPGA-BASED ACCELERATORS
Authors: ZHONG GUANWEN
ORCID iD:   orcid.org/0000-0003-0746-2921
Keywords: FPGA, HLS, Design Space Exploration, Estimation Models, CNNs, Automation
Issue Date: 8-Aug-2017
Source: ZHONG GUANWEN (2017-08-08). DESIGN SPACE EXPLORATION TECHNIQUES FOR FPGA-BASED ACCELERATORS. ScholarBank@NUS Repository.
Abstract: The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve the designer productivity by abstracting the programming effort above register-transfer level. HLS offers various architectural design options with different trade-offs via pragmas. However, non-negligible HLS runtime renders manual or automated HLS-based exhaustive architectural exploration practically infeasible. Moreover, applications containing compute-intensive kernels can effectively leverage FPGAs to exploit fine- and coarse-grained parallelism. HLS tools, however, are inefficient in identifying and exploiting multiple levels of parallelism, thereby producing sub-optimal accelerators. To address these challenges of kernel-level optimizations with HLS, this dissertation focuses on developing effective and efficient HLS and estimator-based design space exploration (DSE) techniques for FPGA-based accelerators. Moreover, as applications become more complex, we present acceleration of convolutional neural networks (CNNs) on FPGA-based heterogeneous architectures as a case study to better understand the system-level challenges and provide insights towards designing such platforms.
URI: http://scholarbank.nus.edu.sg/handle/10635/137752
Appears in Collections:Ph.D Theses (Restricted)

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