Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/13722
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dc.titleOxide bypassed power MOSFET devices
dc.contributor.authorYANG XIN
dc.date.accessioned2010-04-08T10:35:48Z
dc.date.available2010-04-08T10:35:48Z
dc.date.issued2004-02-23
dc.identifier.citationYANG XIN (2004-02-23). Oxide bypassed power MOSFET devices. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/13722
dc.description.abstractThe Superjunction (SJ) MOSFET power device is highly recognized for its higher blocking capability and lower on-resistance that breaks the conventional unipolar silicon limit. However, SJ devices below 100 V rating incur constraint of unrealistic narrower column widths and their performance is greatly handicapped due to difficulties in formation of perfect charge-balanced SJ p-n columns by the current process technology. Alternative approaches of Oxide-Bypassed (OB) SJ MOSFETs are proposed in this thesis. For the first time, Tunable Oxide-Bypassed (TOB) MOSFET technology is reported to provide a feasible solution. The proposed TOB-UMOS device of 79 V rating has been successfully fabricated. Laboratory measurements indicate that the device has broken the ideal SJ MOSFET performance limit, and potentially the ideal silicon limit as well. Moreover, Gradient OB MOSFET is proposed to further improve the performance of OB devices in future investigations.
dc.language.isoen
dc.subjectSuperjunction MOSFET, on-resistance, ideal silicon limit, ideal SJ limit, OB MOSFET, TOB-UMOS
dc.typeThesis
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.supervisorLIANG YUNG CHII
dc.contributor.supervisorSAMUDRA, GANESH S
dc.description.degreeMaster's
dc.description.degreeconferredMASTER OF ENGINEERING
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Master's Theses (Open)

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