Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/13486
Title: Design and simulation of sub-quarter micron MOSFETs
Authors: SREEDHARAN PILLAI SREELAL
Keywords: Grooved gate MOSFET, Parasitic capacitance, Self-aligned gate, Overlap capacitance, Bias dependence, Optimisation
Issue Date: 11-Dec-2003
Source: SREEDHARAN PILLAI SREELAL (2003-12-11). Design and simulation of sub-quarter micron MOSFETs. ScholarBank@NUS Repository.
Abstract: Grooved gate MOSFETS are known to alleviate many of the short-channel and hot-carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. In this work a systematic comparison of all the major electrical characteristics of grooved gate device with conventional planar device is done at gate lengths of 100 nm. An optimised process flow is presented mainly to overcome two of its major drawbacks - higher gate-to-source/drain parasitic capacitance and lack of a self-aligned and integrated gate structure. The resulting device structure exhibits significantly enhanced electrical characteristics. An analytical model for the gate-to-drain and gate-to-source capacitance characteristics of the grooved gate device and its application to the device with effective channel length of 70 nm are then presented. It features an extrinsic capacitance model that incorporates the strong bias dependence of overlap capacitance and leads to better comprehension of the issues involved in optimisation and analysis of not only such novel device structures but source/drain engineered conventional planar devices also.
URI: http://scholarbank.nus.edu.sg/handle/10635/13486
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