Please use this identifier to cite or link to this item: https://doi.org/10.1016/j.mee.2010.01.010
Title: Performance enhancement in Ge pMOSFETs with orientation fabricated with a Si-compatible process flow
Authors: Dutta Gupta, S. 
Mitard, J.
Eneman, G.
De Jaeger, B.
Meuris, M.
Heyns, M.M.
Keywords: Channel-orientation
Enhanced mobility
Germanium (Ge)
pFET devices
Issue Date: Nov-2010
Citation: Dutta Gupta, S., Mitard, J., Eneman, G., De Jaeger, B., Meuris, M., Heyns, M.M. (2010-11). Performance enhancement in Ge pMOSFETs with orientation fabricated with a Si-compatible process flow. Microelectronic Engineering 87 (11) : 2115-2118. ScholarBank@NUS Repository. https://doi.org/10.1016/j.mee.2010.01.010
Abstract: The electrical characterization of Ge pMOSFETs having and orientations with gate lengths of 3 μm have been demonstrated with a Si-compatible process flow. Employment of orientation in Ge pMOSFETs without incorporation of strain provided ∼10% enhancement in effective hole mobility and drive current when compared to oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm2/V s for devices to 210 cm2/V s for the oriented Ge devices at room temperature, which is ∼2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H2 ambient for Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of Dit, improving the transistor performance. These results indicate that the Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications. © 2010 Elsevier Ltd. All rights reserved.
Source Title: Microelectronic Engineering
URI: http://scholarbank.nus.edu.sg/handle/10635/128740
ISSN: 01679317
DOI: 10.1016/j.mee.2010.01.010
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