Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISSCC.2013.6487739
Title: A 0.45V 100-channel neural-recording IC with sub-μW/channel consumption in 0.18μm CMOS
Authors: Han, D.
Zheng, Y.
Rajkumar, R. 
Dawe, G. 
Je, M. 
Issue Date: 2013
Citation: Han, D.,Zheng, Y.,Rajkumar, R.,Dawe, G.,Je, M. (2013). A 0.45V 100-channel neural-recording IC with sub-μW/channel consumption in 0.18μm CMOS. Digest of Technical Papers - IEEE International Solid-State Circuits Conference 56 : 290-291. ScholarBank@NUS Repository. https://doi.org/10.1109/ISSCC.2013.6487739
Abstract: Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction. © 2013 IEEE.
Source Title: Digest of Technical Papers - IEEE International Solid-State Circuits Conference
URI: http://scholarbank.nus.edu.sg/handle/10635/125316
ISBN: 9781467345132
ISSN: 01936530
DOI: 10.1109/ISSCC.2013.6487739
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