FAULT-TOLERANT MULTI-PROCESSOR SYSTEMS FOR NANO-SATELLITES

Abstract

Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Current commerially-off-the-shelf (COTS) FPGAs have not been built to withstand such errors, which are commong in space environments. In this work we propose a three-fold cross-layer solution which is able to handle different types of faults encountered by SRAM-based FPGAs in nanosat payloads. The solutions proposed at each level are independent from the other levels and can provide good fault tolerance. Moreover, the solutions at different levels can run in conjunction with each other without interfering with the operations of one another. These solutions have been implemented and verified on COTS FPGAs and show a very good tolerance to faults.