NOVEL III-V DEVICE ARCHITECTURES FOR APPLICATION IN ADVANCE CMOS LOGIC AND BEYOND

Abstract

III-V MOSFETs are one of the most attractive devices due to their extremely high electron mobility. However, new processes associated with III-V substrates must be simplified, and costs of integration on Si substrate should be reduced. First, ultra-thin-body (UTB) (1 nm-thick) In0.53Ga0.47As channel junctionless n-FET with raised S/D structure and shortest reported gate length (LG) of 6 nm was realized for III-V MOSFETs. Next, process for heteroepitaxial growth of high-quality InxGa1-xAs on Ge fin was developed. A physical modeling to describe the GaAs facets with different Ge fin orientation is proposed and verified experimentally. Finally, to further improve device SCEs, a novel vertically stacked nanowire (NW) CMOS (InAs n-FET and GaSb p-FET) on Si platform was demonstrated using extremely thin buffer layer (sub-120 nm) technology. Our NW devices achieved the best reported ION/IOFF ratio and swing for III-V CMOS integrated on silicon substrate.