Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/105087
Title: Detecting over rejection in testing of integrated circuits
Authors: Chang, T.C.
Gan, F.F. 
Keywords: Bernoulli distribution
Binomial distribution
Cumulative sum control charts
Statistical process control
Issue Date: Jul-2001
Citation: Chang, T.C.,Gan, F.F. (2001-07). Detecting over rejection in testing of integrated circuits. Journal of Quality Technology 33 (3) : 356-364. ScholarBank@NUS Repository.
Abstract: In parallel testing of integrated circuits (IC's), IC's which are conforming in terms of electrical functionality are sometimes incorrectly rejected. This is commonly known as over rejection. Over rejection is due to faulty sockets or failed components of the test hardware system associated with the socket locations. In this paper we propose a two-stage procedure for monitoring socket locations causing an over rejection: in stage one, a binomial test of proportions is used to identify socket locations which are causing an over rejection; in stage two, a cumulative sum scheme is used to monitor the socket locations to detect possible failures of components of the test hardware system. Detection of faulty sockets or failed components results in a reduction of rejected conforming IC's. A simple method is provided for the design of such a procedure. Formulas are also provided which allow the performance of the scheme to be evaluated. An application of the procedure in parallel testing of IC's is performed. A follow up study is conducted to determine practical problems with the procedure and to find solutions.
Source Title: Journal of Quality Technology
URI: http://scholarbank.nus.edu.sg/handle/10635/105087
ISSN: 00224065
Appears in Collections:Staff Publications

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